The race to build faster, smarter AI infrastructure just entered a new chapter. At the Future of Memory and Storage (FMS) 2026 conference in Santa Clara, Samsung Electronics pulled back the curtain on an ambitious slate of next-generation memory technologies. The company's declaration about the future of AI computing was blunt, and literal: up.
The centerpiece of Samsung's presentation was zHBM, a radical new memory architecture that fundamentally reimagines the physical relationship between AI processors and the memory that feeds them. Rather than placing high-bandwidth memory (HBM) alongside an AI accelerator on a silicon interposer, which has been the standard approach across every HBM generation from HBM1 through the upcoming HBM5, zHBM stacks the memory directly on top of the accelerator chip. The "z" in the name refers to the vertical axis. It signals a shift from two-dimensional packaging to a three-dimensional one.
The performance implications, according to Samsung, are staggering. By virtually eliminating the physical distance data must travel between processor and memory, zHBM is projected to deliver roughly eight times the performance of HBM5 on a per-GPU basis, while improving performance-per-watt by up to three times. A new heat-dissipation structure called HPB, applied to the side of the core die, is said to cut thermal resistance by more than half compared to HBM5.
"With the existing packaging structure, there are limits to narrowing the physical distance between the accelerator chip and the memory," said Kyungryun Kim, Vice President and Project Leader of Samsung's DRAM Design Team, during the keynote. The comment underscored the central thesis of the presentation: that conventional side-by-side memory designs are approaching a ceiling, and the only way forward is vertical integration.
Critically, zHBM is designed to support customer-specific configurations. Custom intellectual property can be integrated into an interlayer between the memory stack and the AI accelerator, allowing system designers to tailor capacity and functionality for specific AI workloads. That flexibility will matter as the industry splinters into increasingly specialized training and inference architectures.
Samsung's vision didn't stop at high-bandwidth memory. The company also introduced zNAND-O, a high-performance NAND concept based on its V-NAND technology, available in four-layer and eight-layer configurations. Designed for edge AI systems that need to process large datasets with minimal delay, zNAND-O targets the growing category of on-device AI workloads where sending data to a centralized data center isn't practical.
The performance numbers are eye-catching. Samsung demonstrated that when running a GPT model with 120 billion parameters, zNAND-O matched the token processing speed of a conventional DRAM-based server. The operating cost was one-sixth. That ratio stands to accelerate the push to move large-scale AI inference out of the cloud and closer to the point where data is generated.
Samsung also unveiled V10 BV-NAND (Bonding V-NAND), the 10th generation of its V-NAND line and the first in the industry to use wafer bonding technology for vertical stacking. The result: a device with more than 400 layers and a 58% improvement in memory density over its V9 predecessor. The architecture serves as the production bridge between Samsung's current V9 generation, already in mass production inside the PM1763 enterprise SSD since July, and a longer-term roadmap that envisions a 1,000-layer device by 2030 through multi-wafer bonding.
The FMS booth, designed to resemble an AI cloud server, showcased approximately 30 memory and storage technologies spanning Samsung's entire portfolio. Among the highlights were HBM4E samples, which Samsung became the first company to ship to global customers back in May, and an HBM5 concept model targeting 2028 mass production.
The company also demonstrated LPDDR5X-PIM, described as the industry's first LPDDR memory with processing-in-memory technology. By performing selected data-processing operations within the memory itself, rather than shuttling data back and forth to a processor, the design promises meaningful efficiency gains for suitable AI workloads.
On the enterprise storage front, Samsung spotlighted the PCIe Gen6 PM1763 and the ultra-compact BM1773 enterprise SSD. During the keynote, Samsung executive Jin-Yub Lee held up the BM1773 in person, noting that the single storage chip carries a value comparable to a luxury sedan.
Samsung's FMS 2026 announcements paint a picture of a company swinging aggressively across vertical HBM stacking, edge-optimized NAND, processing-in-memory, and enterprise storage all at once. The goal is clear: stake out leadership in what has become the most consequential technology race of the decade.
What Samsung notably did not announce were firm timelines for zHBM or zNAND-O commercialization, or pricing for the new technologies. These remain concept models, demonstrations of technical capability and strategic intent. Translating them into shipping products at scale will be the real test.
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